Code:
shiftout SI,SCK,MSBPRE,[address\24] ; sends address location for write
Could not get this to work. Set address to long. When I looked at what was being sent I was getting the bytes in the wrong order.
Address variable MSB on left LSB to the right correct?
------------------------------------Address long var---------------------------------
Address.highbyte.highword _ Address.lowbyte.highword _ Address.highbyte.lowword _ Address.lowbyte.lowword
When I used shiftout.....[address\24] I got
Address.highbyte.highword _ Address.lowbyte.highword _ Address.highbyte.lowword
at eeproms si pin
I looked at using highbyte lowbyte ect.. to send the right bytes
Code:
address_temp = address.highword
address_temp2 = address_temp.lowbyte
address_temp = address.lowword
shiftout.....[address_temp2\8, address_temp\16]
I have not gone to far on this route. It seems like alot of variables are needed. It would be nice to do something like
address_temp = address.highword.lowbyte but I don't thik its possable.
My next aproach was to use 3 bytes and if\then to increment the bytes
So changing your example to this
Code:
shiftout SI,SCK,MSBPRE,[0x03\8,cntr\8, cntr1\8, cntr2\8] 'Sends write command along with 24bit address
And adding this
''-------------------------Increments eeprom address by the constant increment--------------------------
Code:
if cntr2 = 255 then
if cntr1 = 255 then
cntr = cntr + increment
cntr1 = 0
else
cntr1 = cntr1 + increment
cntr2 = 0
endif
else
cntr2 = cntr2 + increment
endif
And change this to write to the whole eeprom
Code:
IF cntr = 1 and cntr1 = 255 then _whoa ; reached last EEPROM cell?
This works. The way I visualize it is the eeprom is a book. 2 chapters, 512 pages and 256 lines per page.
cntr = chapters (7msb don't care last bit will be a 1 0r 0) chapter 0 pages 0 - 255 or chapter 1 pages 256 - 512
cntr1 = pages (0 to 255 per chapter)
cntr2 = lines (0 to 255 per page)
Have to make sure not to cross page as data will wrap around to line 0 of same page
On a side note I connected the eeprom so that SO and SI share a pin
Attachment:
eeprom.png [ 8.66 KiB | Viewed 130 times ]
I have tried this using 5 different Nano pins for SO\SI
P3 - eeprom works
P4 - eeprom works
P5 - eeprom works
P8 - eeprom does not work
P9 - eeprom does not work